For many years the trend in semiconductor device and package design was toward ever higher levels of integration, which in memory technology takes the form of integrating memory and logic on the same chip. Power modules and driver circuits are conventionally part of DRAM and SRAM devices, and many memory device designs have application specific logic embedded with the memory arrays on a common chip. However, while logic and memory semiconductor elements share many common features, there are differences. For example, a critical feature of a DRAM memory element is the storage capacitor. This element must be made optimally small, and essentially without defects or leakage. Logic devices have no comparable element, and are more forgiving in many device aspects. Consequently a wafer fabrication process that is tailored for memory device optimization is not usually optimum for logic devices. Thus, compromises are made in order to have different device species on the same semiconductor chip.
An alternative development to "integration or embedding" is the concept of "disintegration", where memory devices consist mainly of memory cells and their necessary support circuits are kept in one chip while the "application" logic and other transistors are put on another chip. These chips can be processed optimally for the size and nature of their components. In this technology, the "integration" is performed at the package level, and the key to its success is a packaging technology that produces a final product that is superior to a chip integrated system in performance and cost, and at least comparable in size.
A leading candidate for this packaging technology is flip chip bonding and assembly. Flip chip bonding is a well developed technology and is characterized by bonding bare silicon IC die upside down on an interconnect substrate such as a printed wiring board. Several bonding techniques have been developed, e.g. ball bonding, ball grid array (BGA--a form of ball bonding), and solder bump bonding. These techniques lead to relaxed I/O pitch through smaller contact surfaces, and area arrays rather than perimeter arrays for chip interconnection sites. Moreover, electrical performance is enhanced because lead lengths are reduced. Typically, the bonding method in these techniques is solder bonding.
Initial implementations of these developments were multi-chip modules in which two or more active device chips are bonded to a common interconnection substrate. The interconnection substrate is a standard printed wiring board, or in more sophisticated packaging designs, a silicon wafer. Most of the circuitry that provides intra chip interconnections, i.e. connections between chips, is formed on the interconnection substrate. The chips themselves contain inter chip interconnections in the form of circuits (metallization) within the chips.
The metallization terminates in arrays of I/O bonding sites which are the interconnection sites for intra chip interconnections. With state of the art logic and memory chips having dozens or hundreds of I/O sites to interconnect, the intra chip interconnections on the interconnection substrate become very complex. In current designs, this circuitry requires many crossover interconnects. To provide crossovers in the intra chip interconnections, a second level of printed circuits is typically provided. Multi-level printed circuit boards, and multi-level silicon interconnection substrates are well known and widely used, but are still more expensive, and provide less versatility, than single level interconnection arrangements.
A more recent advance in multi-chip module technology is the chip-on-chip approach where an active chip is flip-chip bonded to another active chip rather than to an interconnection substrate. When the relative sizes of the chips allows, two or more small chips can be bonded to a larger chip. Logic chips, e.g. digital signal processors, are quite large with a footprint sufficient to contain at least two standard memory chips. The logic chip, i.e. the support chip, is packaged in a lead frame package thus eliminating the board or interconnection substrate of more conventional MCM packages. The intra chip interconnection circuitry in the chip-on-chip package is typically constructed on the surface of the support chip. However, the same limitations arise as discussed above, i.e. crossover connections are frequently required, and the support chip must then be provided with two levels of interconnections.
Multi-level interconnection assemblies are well known and widely used, but are still more expensive, and provide less versatility, than single level interconnection arrangements.